The present disclosure relates generally to a transmission and reception of signals, and more specifically to mitigating inter-symbol interference (ISI) in low power, high speed data rate environments.
Equalization techniques may be used in connection with a transmission or reception of signals. For example, in connection with a channel (e.g., a copper transmission line) linking integrated circuits and memories on a printed circuit board (PCB), dielectric losses and impedance mismatches associated with the channel may cause signal attenuation and dispersion, which may result in undesirable inter-symbol interference (ISI).
To combat ISI in designs, such as low-power high-speed I/O link designs, feed-forward equalization (FFE) may be implemented in connection with a transmitter. Implementation of an FFE in the transmitter has the benefit of working with a known data sequence with samples that are available in a digital format. Implementing an FFE in a receiver may be more difficult since such an implementation requires, with respect to an input or received signal xin, the use of one or more analog delay cells 102, where the outputs of the analog delay cells 102 may be weighted via weights 104 and summed to generate an output yout as shown in FIG. 1. Implementation of an FFE in the receiver, however, may provide a benefit of immunity with respect to timing jitter amplification in the channel. As data rates increase and lower-power technologies are utilized, the effects of the channel become increasingly pronounced on the quality of the received signal.